STR9104 FEATURES

● 32-bit RISC Core

• Higher performance ARM922-compatible RISC (with 16kB I-cache, 16kB D-cache, 8kB I-scratchpad, 8kB D-scratchpad) memory and memory management unit(MMU) for high-level RTOS, with programmable CPU core clocks up to 200MHz
• Proprietary advanced system bus architecture achieving superior performance
• Supports TRACE32 and Multi-ICE JTAG debugging interfaces
• Built-in intelligent power management for normal and power-saving mode of operations
• Support IRQ/FIQ interrupt modes
• Support little-endian ordering

● Network Processing Engines

• Embedded 2-port 10Base-T/100Base-TX MAC’s with 4-port L2 switch engine for wire-speed broadband switch application, compliant with 802.3-2002
• Hardware-based network address translation (HNAT) accelerator supporting L3/L4 fast-path routing to off-load CPU
• DMA engines with burst mode support for efficient data transfer among CPU and WAN/LAN ports
• 1K entries address lookup table
• Support IPv4 packet filtering and TCP/UDP/IP checksum off-load for incoming and outgoing packets

● External Memory Interface

• Static Memory: support 8/16-bit programmable external bus width with address range up to 16 Mbytes, for ROM/Flash/SRAM
• DDR SDRAM: 16-bit data path widths with address range up to 256Mbytes

● External Peripheral Interface

• Two MII/Reverse MII interfaces (MAC or PHY mode) for external transceivers or single-chip switch
• Embedded USB2.0-compliant host PHY and EHCI/OHCI controller supporting two external USB devices simultaneously for low-/full-/ high-speed operations(for wireless module and storage)
• High-speed 16C550-compliant UART serial channel supporting configurable baud-rates up to 1.5Mbps for monitor console or data transport interface with hardware CTS/RTS flow control (for Bluetooth radio module, etc.)
• 8/16-bit external I/O interface supporting PCMCIA interface or generic DSP/CPU host interfaces (for commercial-off-the-shelf VoIP DSP co-processor, etc.)
• 21 individually programmable GPIO’s (shared with other function pins)

● Other Function Blocks

• Two 32-bit programmable timers, one watch-dog timer and one real-time counter (RTC)
• Programmable interrupt controller with FIQ/IRQ priority configurable
• Integrated PLL clock synthesizer generates all the required clocks from a single 25MHz reference input
• Optimized on-chip voltage regulator provides 2.5/1.8V supplies with low-cost external PNP pass transistors

● Electrical CharacteristicsPackage: LFBGA-257 (14mm*14mm)

• 0.18um low-power design with intelligent power management
• Single 3.3V supply: 3.3V for general I/O’s, 2.5V for DDR I/O’s, and 1.8V for core logic and embedded analog PLL’s

● Targeted Applications

• Wireless/wired home gateway, SOHO router
• Home media/entertainment gateway
• Printer server
• Home Network Attachment Storage (NAS)

● Software Supports

• Linux and Nucleus BSP supports
• Technical documents